3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

TLDR

3D integration using through‑silicon vias and low‑volume lead‑free solder enables high‑bandwidth, fine‑pitch, short‑distance interconnections and can be achieved via chip‑to‑chip, chip‑to‑wafer, or wafer‑to‑wafer stacking, with chip‑to‑chip and chip‑to‑wafer allowing known‑good die stacking for higher yields. The authors aim to evaluate chip‑to‑wafer integration as a near‑term high‑yield, high‑performance solution, while anticipating wafer‑to‑wafer integration as a future high‑throughput, high‑yield manufacturing strategy. They assembled and characterized stacks of up to six dies interconnected with lead‑free solder vias less than 6 µm tall. The chip‑to‑wafer 3D integration produced an average TSV resistance of only 21 mΩ, demonstrating the effectiveness of the fine‑pitch lead‑free solder interconnects.

Abstract

Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ.