Demonstration of memory string with stacked junction-less SONOS realized on vertical silicon nanowire

Abstract

We demonstrated a NAND memory string based on 2-level stacked junction-less (JL) gate-all-around (GAA) SONOS cells fabricated on vertical Si nanowire (SiNW) platform with footprint of 6F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /2. The stacked SiNW memory cells with channel dimension down to 30nm exhibit well-behaved memory characteristics such as program/erase (P/E) speeds, endurance, retention and program disturb properties. The vertically stacked device structure improves the bit density and the absence of junctions reduces the process complexity/cost and makes this device manufacturable with very low thermal budget.