An SEM based system for a complete characterization of latch‐up in CMOS integrated circuits

Abstract

Abstract An electron beam testing system was established for a complete and detailed analysis of latch‐up in CMOS integrated circuits. Problems which can be studied include: identification of latch‐up current paths in steady state condition; measurement of the local latch‐up sensitivity of the various parts of the circuit; observation of the time evolution of latch‐up from the firing event to the final condition.