IEEE Journal of Solid-State Circuits · 2014 · 22 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsClock ManagementDynamic Power ReductionLow-power Digital Circuit DesignMemory Subsystem DesignMixed-signal IntegrationTiming AnalysisDuty Cycle CorrectionJitter MitigationMemory Interface ArchitectureMemory Interface Design
A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy efficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side that wakes up from 0 mW and locks within 3 clock cycles consuming 24 mW with residual timing error less than 33 mUI. Following initial lock, the DLL operates in a closed loop to compensate for V,T drift consuming 6 mW @ 1.6 GHz including a replica buffer. By incorporating an injection locked oscillator inside the loop, the DLL provides PLL like high frequency input jitter filtering, and corrects ±10% DCD without an additional duty cycle correction loop.
9