Variability analysis and FinFET-based design of XOR and XNOR circuit

Abstract

Due to aggressive scaling and process imperfection in sub-45 nm technology node V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> (threshold voltage) shift is more pronounced causing large variations in circuit response. Therefore, this paper presents the analyses of various popular XOR/XNOR circuits in light of PVT (process, voltage and temperature) variations to verify their functionality and robustness. This paper first investigates output levels of various XOR/XNOR circuits. It further analyses those XOR/XNOR circuits offering better output levels in terms of delay and energy-delay product (EDP). It also performs variability analysis of those parameters to determine robustness of the XOR/XNOR designs. Finally, it implements the best XOR/XNOR circuit in emerging FinFET technology to achieve even better results in terms of propagation delay and EDP. The proposed FinFET-based implementation of XOR/XNOR circuit offers 1.4× improvement in delay and 1.8× improvement in EDP compared to its CMOS counterpart. It proves to be immune against process variation. It proves its robustness by offering 19.3× improvements in delay variability and 10.8× improvements in EDP variability.