A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias

Matt Wordeman, J. A. Silberman, Gary Maier, M. Scheuermann

2012 · 49 citations · 3 references

Concepts

TL;DR

3D integration promises improved system performance by increasing interconnect bandwidth, and a processor stacked with cache memory is a key application. This work presents the design and operation of a prototype 3D system that stacks an eDRAM memory layer, IBM Power7 L3 cache logic blocks, and a processor proxy layer with through‑silicon vias. The stack is built with 50 µm pitch μC4 interconnects linking the front side of a thick chip to Cu‑filled TSVs (~20 µm diameter, <100 µm deep) on the back side of a thinned chip.

Abstract

3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth [1]. A processor stacked with cache memory is one potential application of 3DI [2]. This work describes the design and operation of a prototype of a 3D system, constructed by stacking a memory layer, built with eDRAM [3] and logic blocks from the IBM Power7™ processor L3 cache, and a "processor proxy" layer in 45nm CMOS technology [4] enhanced to include through-silicon vias (TSVs) [5]. Unlike the previously reported 3D eDRAM [6], the 3D stack described here is constructed using 50μm pitch μC4's joining the front side of one thick chip to TSV connections on the back side of a thinned chip. TSVs are formed of Cu-filled vias that are ~20μm in diameter and <;100μm deep [5].

References

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