Half-V/sub CC/ sheath-plate capacitor DRAM cell with self-aligned buried plate wiring

Abstract

A trench-capacitor DRAM cell called a half-V/sub CC/ sheath-plate capacitor (HSPC) cell has been developed using 0.6- mu m-process technology. It is applicable to DRAMs with capacities of 16 Mb and over. The HSPC cell achieves a storage capacitance of 51 fF in a cell area of 4.2 mu m/sup 2/ and excellent immunity (critical charge Q/sub c/<35 fC) against alpha-particle injection. These advantages are achieved using a half-V/sub CC/ sheath-plate structure, a 5.5-nm SiO/sub 2/-equivalent Si/sub 3/N/sub 4/-SiO/sub 2/ composite film, and three self-alignment technologies involving buried plate wiring, a sidewall contact and a pad for the bit-line contact. The device performance is evaluated using an experimental 2-kb array.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>