2012 · 14 citations · 6 references
EngineeringElectrical EngineeringManufacturing ProcessesMicroelectronicsSemiconductor DevicesChip PackagingCmos Circuit DesignIntegrated Circuit DesignIntegrated Circuit DevicesIntegrated Circuit FabricationInterconnect Technology3D Integrated CircuitsCircuit IntegrationCmos Fabrication ProcessesThree-dimensional Integrated Circuit InterconnectsThree-dimensional Integrated Circuit LayoutThree-dimensional IntegrationThrough-silicon Via DesignThrough-silicon Vias
This study focuses on the prototype of a 3D circuit in 65nm CMOS node, in which digital and analog functions have been partitioned on two different layers, assembled in a face-to-face integration and reported on a BGA. The paper more specifically presents the process technology carried out for the realization of the bottom die. Major process steps are described and evaluated from an electrical performance point of view.
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Advances, challenges and opportunities in 3D CMOS sequential integration
P. Batude, M. Vinet, B. Prévitali et al. · 2011 · 148 citations · Full text
Resistance increase due to electromigration induced depletion under TSV
Thomas Frank, C. Chappaz, Philip R. LeDuc et al. · 2011 · 73 citations
Integration of a temporary carrier in a TSV process flow
Jean Charbonnier, S. Chéramy, David Henry et al. · 2009 · 61 citations
Investigation on TSV impact on 65nm CMOS devices and circuits
H. Chaabouni, Maxime Rousseau, Philip R. LeDuc et al. · 2010 · 54 citations
Engineering, Computer Engineering, Electrical Engineering +17