Failure Analysis of Superjunction VDMOS Under UIS Condition

Abstract

The failure mechanisms for two kinds of the 750-V Superjunction VDMOS (SJ-VDMOS) devices with different charge imbalance conditions (Qp <; Qn and Qp > Qn) under unclamped inductive switching (UIS) condition are investigated in detail by experiments and 2-D devices simulations in this paper. For Qp <; Qn, only the channel current appears in the device during the UIS turn-off process, and the avalanche current appears after the device turns off. Finally, the parasitic transistor of the device is triggered when the drain voltage reaches the BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> , so the device fails. Unlike Qp <; Qn, the SJ-VDMOS device fails before its drain voltage reaches the BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> for the condition of Qp > Qn. Not only the channel current but also the avalanche current caused by ON-state breakdown appears during the UIS turn-off process until the gate voltage decreases below the threshold voltage in the SJ-VDMOS device. The avalanche current flows beneath the n+ region and leads to the activation of the parasitic transistor.