2010 · 18 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsVlsi DesignCmos Circuit DesignDevice ReliabilityNoise In Electronic DevicesNoise In Semiconductor DevicesTiming AnalysisTiming ModelingDynamic StabilityMemory Circuit DesignNoise MarginsNon-volatile Memory DesignRing OscillatorsStatic Noise MarginStatic Random-access Memory DesignTunable Oscillators
SRAM yield is often characterized through distributions of static read or write margins [1] [2]. These measurements are analog and therefore can be slow and provide a limited dataset. Distributions of per-cell minimum operating voltages can be characterized rapidly, however, and are often taken as a proxy to static noise margins. Both methods have a common limitation in that the characterization is done statically, thus ignoring any possible effects that may affect dynamic operation. Pulsed ring oscillators for evaluating SRAM cell read timing have been previously proposed [3]. In contrast, tunable ring oscillators (RO) for characterizing dynamic cell stability during write and read operations without the need to modify the SRAM array are demonstrated in this work. The performance variation is captured as a spread in RO operating frequencies and therefore can be obtained rapidly.
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SRAM cell design for stability methodology
C. Wann, Robert Wong, David Frank et al. · 2005 · 149 citations
Engineering, Computer Engineering, Electrical Engineering +10
Large-scale read/write margin measurement in 45nm CMOS SRAM arrays
Zheng Guo, Andrew E. Carlson, Liang-Teck Pang et al. · 2008 · 52 citations
Engineering, Computer Engineering, Electrical Engineering +17