Dynamics of heavy-ion-induced latchup in CMOS structures

Abstract

Heavy-ion-particle-induced latchup phenomenon in CMOS parasitic p-n-p-n structures is analyzed using a two-dimensional transient device simulator. In the study, the dynamics of the latchup turn-on behavior in a conventional bulk structure are investigated in detail. Moreover, the relation between the terminal currents and the behavior of inner variables such as carriers and potential is also described. Relative latchup immunity for several device structures is also studied. From the points of the decoupling of the parasitic n-p-n and p-n-p transistors, which is the key factor for preventing latchup, the p/sup -/-p/sup +/ epitaxial wafer with and without guard bands is discussed in comparison with the conventional structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>