Crosstalk fault modeling in defective pair of interconnects

Fault modeling and simulation for crosstalk in system-on-chip interconnects

Michael Cuviello, Sujit Dey, Xiaoliang Bai et al. · International Conference on Computer Aided Design · 1999 · 192 citations

Engineering, Computer Engineering, Electrical Engineering +17

Analysis of on-chip inductance effects for distributed RLC interconnects

Kaustav Banerjee, A. Mehrotra · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2002 · 173 citations

Engineering, Computer Engineering, Electrical Engineering +17

Fault modeling and simulation for crosstalk in system-on-chip interconnects

Michael Cuviello, S. Dey, Xiaoliang Bai et al. · 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) · 2003 · 162 citations

Engineering, Computer Engineering, Electrical Engineering +17

Defective Behaviours of Resistive Opens in Interconnect Lines

Daniel Arumí, R. Rodríguez‐Montañés, Joan Figueras · 2005 · 41 citations

Engineering, Computer Engineering, Electrical Engineering +17

An Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges

Gang Chen, S.M. Reddy, Irith Pomeranz et al. · 2005 · 39 citations

Engineering, Computer Engineering, Electrical Engineering +17