Defective Behaviours of Resistive Opens in Interconnect Lines

Abstract

Defective interconnect lines affected by open defects have been intentionally designed and introduced on a CMOS digital test circuit. A simple bus structure with a scan register followed by a hold register and two buffers is used to investigate the influence of the crosstalk capacitances of the adjacent lines to the open defect. The strength of the open defect has been varied within a realistic range of resistances going from a full (complete) open up to a weak (low-resistive) open. The static and dynamic behavior of the defective lines have been electrically characterized taking into account the location of the defect as well as its resistive value. This characterization allows the extraction of general information useful for the prediction and detection of the faulty behavior caused by the defect. Testability conditions of this defect in interconnect lines are discussed.