SP-HV: A Scalable Surface-Potential-Based Compact Model for LDMOS Transistors

Abstract

This paper introduces a scalable compact model of lateral double-diffused MOS (LDMOS) transistors. The new model, i.e., the Surface-Potential-based High-Voltage MOS (SP-HV), is constructed from a surface-potential-based bulk MOS field-effect transistor model, i.e., PSP, and a nonlinear resistor model, i.e., R3. Extensions are made to both PSP and R3 for improved modeling of LDMOS devices, and one internal node is introduced to connect the two component models. The new model is validated by comparison to technology computer-aided design (TCAD) simulations and experimental data. Quasi-saturation, self-heating, impact ionization current in the drift region, and complex behavior of transcapacitances are accurately modeled by SP-HV.