IEEE Journal of Solid-State Circuits · 2004 · 83 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignEmbedded Memory BlocksIntegrated Circuit DesignLeakage Power ReductionMemory DevicesPower ManagementGate LeakageGate Leakage CurrentGate Oxide LeakageGate Oxide Leakage ReductionLeakage CurrentLeakage Current ReductionMemory ArraysTunneling Current
In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local dc level control (LDLC) for SRAM cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and fabricated a 32-kB 1-port SRAM using 90-nm CMOS technology. The six-transistor SRAM cell size is 1.25 /spl mu/m/sup 2/. Evaluation shows that the standby current of 32-kB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.
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Physics of Semiconductor Devices
Samarth Jain, S. Radhakrishna · 1987 · 4.2K citations
A low power SRAM using auto-backgate-controlled MT-CMOS
Koji Nii, Hiroshi Makino, Yoshiki Tujihashi et al. · 1998 · 115 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17