Koichiro Ishibashi

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

S. Ohbayashi, Makoto Yabuuchi, Koji Nii et al. · IEEE Journal of Solid-State Circuits · 2007 · 150 citations

System On Chip, Electrical Engineering, Local Variability +10

A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias

M. Miyazaki, Go Ono, Koichiro Ishibashi · IEEE Journal of Solid-State Circuits · 2002 · 126 citations

Low-power Electronics, Electrical Engineering, Engineering +10

16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

Kensuke Osada, Y. Saitoh, Eishi Ibe et al. · IEEE Journal of Solid-State Circuits · 2003 · 93 citations

Hardware Security, Electrical Engineering, Engineering +15

Universal-V/sub dd/ 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Kensuke Osada, Jinuk Luke Shin, MD Shahrukh Adnan Khan et al. · IEEE Journal of Solid-State Circuits · 2001 · 81 citations

Hardware Security, Low-power Electronics, Electrical Engineering +14

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

K. Sasaki, Koichiro Ishibashi, Kazuhiro Ueda et al. · IEEE Journal of Solid-State Circuits · 1992 · 55 citations

Non-volatile Memory, Engineering, Vlsi Design +18