2012 · 18 citations · 13 references
EngineeringComputer ScienceElectrical EngineeringAnalog ElectronicsMachine LearningTest DevelopmentComputational ModelingDesign For TestabilityElectrical System TestingNonlinear Circuit AnalysisAnalog TestabilityNonlinear CircuitsState Space ExplorationState-space StructureStimulus GenerationTest Case GenerationTest CasesTest Generation
We present a methodology to generate goal-oriented test cases for verifying nonlinear analog circuits. We use a learning-based approach to identify the goal regions in circuit's state space. We use the information that we learn to guide the growth of Rapidly-exploring Random Trees (RRTs) towards these goal regions. Compared to previous approaches for test generation, our methodology generates several test cases of the circuit that are more concentrated in the relevant operating regions. We demonstrate the effectiveness of our approach on typical case studies. We show that our methodology can be used to generate test cases for undesirable behavior that was previously hard to detect.
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Automatic symbolic verification of embedded systems
Rajeev Alur, Thomas A. Henzinger, Pei -Hsin Ho · 2002 · 115 citations