Noise-tolerance improvement in dynamic CMOS logic circuits

Abstract

Dynamic CMOS logic styles are widely used in high-performance systems due mainly to their speed. However they have lower noise-tolerance than their static CMOS counterparts. To overcome this disadvantage a new noise-tolerant circuit technique, suitable for precharge-evaluate dynamic circuits, is presented. The technique is suitable for TSPC and domino gates. Comparisons with previously reported noise-tolerant dynamic circuit techniques are presented. Simulation results on TSPC and domino gates show that the proposed technique improves the noise tolerance of conventional dynamic gates with reduced performance overhead. The feasibility of this new technique is demonstrated by means of a pipelined 0.35 μm CMOS carry look-ahead full adder. Experimental results show an increased noise tolerance of up to three times over standard CMOS logic.