The future of wires

R. Ho, Ken Mai, Mark Horowitz

Proceedings of the IEEE

Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignVlsi Architecture +13

Smart Memories

Ken Mai, Tim Paaske, Nuwan Jayasena, +3

Hardware SecurityElectrical EngineeringEngineeringSmart Memories ChipSmart Memories +11

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Yu Cai, Yixin Luo, Erich F. Haratsch, +2

Flash Memory ErrorsCharge LeakageElectrical EngineeringNon-volatile MemoryEngineering +12

Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

Eric S. Chung, Peter Milder, James C. Hoe, +1

Heterogeneous ComputingEngineeringEnergy EfficiencyComputer ArchitectureEducation +19

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

Jangwoo Kim, Nikos Hardavellas, Ken Mai, +2

International Symposium on Microarchitecture

Hardware SecurityNon-volatile MemoryMemory ArchitectureEngineeringError Control Technique +13

Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime

Yu Cai, Gülay Yalçın, Onur Mutlu, +4

Storage PerformanceEngineeringRetention-aware Error ManagementComputational StorageComputer Architecture +17

Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling

Yu Cai, Erich F. Haratsch, Onur Mutlu, +1

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013

Non-volatile MemoryElectrical EngineeringEngineeringThreshold Voltage DistributionEmerging Memory Technology +10

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

Benton H. Calhoun, Yu Cao, Xin Li, +4

Proceedings of the IEEE

EngineeringVlsi DesignNanocomputingWell-designed CircuitsPhysical Design (Electronics) +16

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Yu Cai, Onur Mutlu, Erich F. Haratsch, +1

Hardware SecurityNon-volatile MemoryEngineeringThreshold Voltage DistributionProgram Analysis +9

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

Jangwoo Kim, Nikos Hardavellas, Ken Mai, +1

Hardware SecurityNon-volatile MemoryMemory ArchitectureEngineeringError Control Technique +13