Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

TLDR

Single‑chip heterogeneous computing can improve energy efficiency by combining traditional processors with unconventional cores such as custom logic, FPGAs, or GPGPUs, but future bandwidth scarcity may limit these benefits. The study aims to extend performance scaling of future chip multiprocessors while prioritizing energy efficiency, and to evaluate the relative merits of different U‑core approaches under technology constraints. The authors develop a model that extends prior heterogeneous multicores models by incorporating less‑obvious relationships between conventional processors and diverse U‑cores, supports speculation of future designs using ITRS scaling trends, and derives U‑core parameters from measured performance and power of tuned applications on current state‑of‑the‑art multicores, GPUs, FPGAs, and ASICs. Our results reinforce current understandings of U‑core potential and limitations and provide new insights into their relative merits.

Abstract

To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing has the potential to achieve greater energy efficiency by combining traditional processors with unconventional cores (U-cores) such as custom logic, FPGAs, or GPGPUs. Although U-cores are effective at increasing performance, their benefits can also diminish given the scarcity of projected bandwidth in the future. To understand the relative merits between different approaches in the face of technology constraints, this work builds on prior modeling of heterogeneous multicores to support U-cores. Unlike prior models that trade performance, power, and area using well-known relationships between simple and complex processors, our model must consider the less-obvious relationships between conventional processors and a diverse set of U-cores. Further, our model supports speculation of future designs from scaling trends predicted by the ITRS road map. The predictive power of our model depends upon U-core-specific parameters derived by measuring performance and power of tuned applications on today's state-of-the-art multicores, GPUs, FPGAs, and ASICs. Our results reinforce some current-day understandings of the potential and limitations of U-cores and also provides new insights on their relative merits.