Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime

TLDR

NAND flash scaling and multi‑level cell technology have made flash storage ubiquitous, yet its bit‑error rate rises sharply with program/erase cycles, and stronger error‑correcting codes offer diminishing returns and high overheads. This work aims to create techniques that tolerate high error rates without relying on prohibitively strong ECC. The proposed Flash Correct‑and‑Refresh (FCR) method periodically reads, corrects, and reprograms or remaps data before retention‑induced charge loss exceeds the correction capability of simple ECC. Simulations based on real‑chip error data show that FCR yields an average 46× lifetime extension across workloads at no additional hardware cost, surpassing what stronger ECC can achieve.

Abstract

With the continued scaling of NAND flash and multi-level cell technology, flash-based storage has gained widespread use in systems ranging from mobile platforms to enterprise servers. However, the robustness of NAND flash cells is an increasing concern, especially at nanometer-regime process geometries. NAND flash memory bit error rate increases exponentially with the number of program/erase cycles. Stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. The goal of this paper is to develop new techniques that can tolerate high bit error rates without requiring prohibitively strong ECC. Our techniques, called Flash Correct-and-Refresh (FCR) exploit the observation that the dominant error source in NAND flash memory is retention errors, caused by flash cells losing charge over time. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that our techniques provide 46× average lifetime improvement on a variety of workloads at no additional hardware cost. We also find that our techniques achieve lifetime improvements that cannot feasibly be achieved with stronger ECC.