Concepedia

Design and test of large embedded memories: An overview

IEEE Design & Test of Computers · 2001 · 102 citations · 9 references

Concepts

Hardware SecurityElectrical EngineeringLarge On-chip MemoriesEngineeringMem TestingComputer EngineeringMemoryComputer ArchitectureLarge Embedded MemoriesMemory DeviceParallel ComputingMicroelectronicsMemory ArchitectureMulti-channel Memory ArchitectureMemory Redundancy

Abstract

Large on-chip memories are desirable but difficult to implement. Challenges range from design automation to fabrication to test algorithms and memory redundancy and repair.

References

9

Using march tests to test SRAMs

A.J. van de Goor · IEEE Design & Test of Computers · 1993 · 270 citations

Hardware Security, Memory Architecture, Reliability Engineering +15

A built-in self-repair analyzer (CRESTA) for embedded DRAMs

Takeshi Kawagoe, J. Ohtani, M. Niiro et al. · 2002 · 170 citations

Hardware Security, Reliability Engineering, Engineering +11

Serial interfacing for embedded-memory testing

Benoit Nadeau-Dostie, A.L. Silburt, V.K. Agarwal · IEEE Design & Test of Computers · 1990 · 148 citations

Engineering, Mem Testing, Computer Architecture +18

Processor-based built-in self-test for embedded DRAM

J. Dreibelbis, J. Barth, H.L. Kalter et al. · IEEE Journal of Solid-State Circuits · 1998 · 84 citations

Hardware Security, Memory Architecture, Engineering +14

Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm

S. Nakahara, K. Higeta, Makiko Kohno et al. · 2003 · 63 citations

Engineering, Mem Testing, Computer Architecture +18