Industrial evaluation of stress combinations for march tests applied to SRAMs

Abstract

This paper presents the results of ten well-known memory test algorithms and four memory test primitives applied to 3876 256 Kbit SRAM chips, using 128 different stress combinations with each test algorithm. The results show that stress combinations influence the coverage of the test algorithms for these SRAMs, and that the influence is less for these SRAMs than for DRAMs. Selecting the right stress combination allows for using a simpler algorithm. The simple memory test primitives can detect all faults given the proper stresses. Power supply voltage turns out to be a very important non-algorithmic stress.