Memory March Testing

Memory March Testing is a Built-In Self-Test method that systematically verifies memory functionality by applying a sequence of controlled read and write operations across memory locations in a marching pattern to detect structural faults such as stuck-at, transition, and coupling defects.

75

Publications

2.7K

Citations

116

Authors

51

Institutions

Publications per year

2017–2026

1

Variants

March Testing

Authors

116

  1. AV
    A.J. van de Goor

    Delft University of Technology, Netherlands

    19 publications · 1.1K citations

    15

    h-index

  2. PG
    Patrick Girard

    Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France

    8 publications · 286 citations

    8

    h-index

  3. AV
    A. Virazel

    Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France

    8 publications · 286 citations

    8

    h-index

  4. SP
    S. Pravossoudovitch

    Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France

    7 publications · 270 citations

    7

    h-index

  5. LD
    Luigi Dilillo

    Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France

    6 publications · 254 citations

    6

    h-index

1–5 of 116

Venues

  1. IEEE Transactions on Computers

    6 publications · 309 citations

    6

    h-index

  2. 3

    h-index

  3. Journal of Electronic Testing

    JETTA · 3 publications · 86 citations

    3

    h-index

  4. 2

    h-index

  5. 1

    h-index

1–5