A 0.18 μm logic-based MRAM technology for high performance nonvolatile memory applications

Abstract

This paper discusses the fabrication of a 2 Kb array test chip with a 1.66 /spl mu/m/sup 2/ cell and a corresponding 128 Kb MRAM (Magnetoresistive Random Access Memory) with a 1.4 /spl mu/m/sup 2/ cell. The technology features a 1 transistor 1 MTJ (Magnetic Tunnel Junction) cell in a 0.18 /spl mu/m, 3 level Cu metallization logic-based process. Outlined here is a yield analysis of the read operation, which is governed by the MTJ resistance distribution function and a systematic study of the write operation. MRAM functionality, with a checkerboard disturb pattern, was obtained after process optimization. Write endurance tests did not show degradation of the cell properties.