IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1988 · 67 citations · 21 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceFault-tolerant ComputingFault-tolerant SystemsBuilt-in Self-testCombinational Logic DescriptionDesign For TestabilityDigital Logic DesignLogic SynthesisAutomatic Test Pattern GenerationCombinational Logic DesignCyclic CodesDigital Circuit Self-testingHardware Overhead AnalysisLinear Feedback Shift RegistersLogic Built-in Self-test
Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in each cone of logic driving a single output are guaranteed to be detected. Examples indicate that LFSRs based on cyclic codes have lower hardware cost and shorter or comparable test lengths than other approaches. These test-pattern generators are well suited to applications where short testing time, low hardware overhead, and 100% single-stuck-at fault coverage are required.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Syndrome-Testable Design of Combinational Circuits
Savir · IEEE Transactions on Computers · 1980 · 208 citations
Wagner, Chin, McCluskey · IEEE Transactions on Computers · 1987 · 147 citations
Engineering, Computer Engineering, Electrical Engineering +11