Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies

Abstract

The increased device variations, lower supply voltages have enforced the usage of write-assist circuits in static random access memory (SRAMs) in the nano-complementary metal oxide semiconductor (CMOS) regime. Negative bit-line scheme during write has been found one of the most promising write-assist solutions. A new low power, negative bit-line scheme is presented. The presented negative bit-line technique can be used to improve the write ability of 6 T single-port (SP) as well as 8 T dual-port (DP) and other multiport SRAM cells. Negative voltage is generated on-chip using capacitive coupling. Only the bit-line on which a ‘0’ is to be written is taken negative during write operation. The proposed circuit design topology does not affect the read operation for bit-interleaved architectures enabling high-speed operation. Simulation results and comparative study of the present scheme with state-of-the art conventional schemes proposed in the literature for 45 nm CMOS technology show that the proposed scheme is superior in terms of process-variations impact, area overhead, timings and dynamic power consumption.