IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009 · 78 citations · 15 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ReliabilityDevice SimulationIntegrated Circuit DesignMemory DevicesShort-channel EffectsCapacitive CouplingFailure ProbabilityFailure Probability AnalysisLow-power Memory CircuitsLow-voltage Cmos DesignMemory Circuit DesignNon-volatile Cmos MemoryNon-volatile Memory Design
Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> X reduction in the Write-failure probability with the proposed method.
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