Ching-Te Chuang - Concepedia

Author

Ching-Te Chuang

IBM Research - Thomas J. Watson Research Center

Also Known As

Ching-Te Chuang, Ching-Te Chuang Ching-Te Chuang, Ching-te Chuang

126

Publications

1.7K

Citations

H-Index

Concepts

All Affiliations

IBM Research - Thomas J. Watson Research Center National Yang Ming Chiao Tung University IBM (United States)Purdue University West Lafayette Georgia Institute of Technology

About

Ching-Te Chuang is an author at IBM Research - Thomas J. Watson Research Center specializing in electrical engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	23	52	1.4K
2	Applied Physics	16	21	629
3	Business	2	2	40
4	Education	2	2	66
5	Biomedical Engineering	2	2	26

Ching-Te Chuang

Publications

1.5K

Citations

H-Index

Page 1

	Year	Citations
SOI for digital CMOS VLSI: design considerations and advances Ching-Te Chuang, Pong-Fe Lu, C.J. Anderson Proceedings of the IEEE Hardware SecurityNon-volatile MemoryElectrical EngineeringLogic ApplicationsEngineering	1998	114
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage Saibal Mukhopadhyay, Rahul Rao, Jae‐Joon Kim, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Hardware SecurityNon-volatile MemoryElectrical EngineeringTransient Negative VoltageEngineering	2009	76
Design and CAD Challenges in sub-90nm CMOS Technologies Kerry Bernstein, Ching-Te Chuang, Rajiv Joshi, International Conference on Computer Aided Design Low-power ElectronicsElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi Design	2003	73
High-performance SRAM in nanoscale CMOS: Design challenges and techniques Ching-Te Chuang, Saibal Mukhopadhyay, Jae‐Joon Kim, Records of the IEEE International Workshop on Memory Technology, Design, and Testing	2007	61
A 400-MHz S/390 microprocessor Charles F. Webb, C.J. Anderson, L. Sigal, IEEE Journal of Solid-State Circuits Hardware SecuritySystem On ChipElectrical EngineeringChip SizeEngineering	1997	55
Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure Saibal Mukhopadhyay, Keunwoo Kim, K.A. Jenkins, On-chip Measurement MethodsEngineeringProcess InstrumentationMeasurementAnalog Design	2007	52
Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits Ming-Long Fan, Vita Pi‐Ho Hu, Yin-Nien Chen, IEEE Transactions on Electron Devices Planar Bulk DevicesElectrical EngineeringFinfet DeviceEngineeringPhysics	2012	48
Design and CAD challenges in sub-90nm CMOS technologies K. Bernstein, Ching-Te Chuang, Ruchir Puri ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486) Low-power ElectronicsElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi Design	2003	48
Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell Subhas Chandra Mukhopadhyay, D. Plass, Y.H. Chan, Non-volatile MemoryElectrical EngineeringVariability AnalysisVlsi DesignEngineering	2004	43
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs Chien-Yu Hsieh, Ming-Long Fan, Vita Pi‐Ho Hu, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignSynchronous Design	2011	43

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