Rahul Rao

Statistical analysis of subthreshold leakage current for VLSI circuits

Rahul Rao, Ashish Srivastava, David Blaauw et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2004 · 192 citations

Engineering, Computer Engineering, Electrical Engineering +17

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability

Aditya Bansal, Rahul Rao, Jae‐Joon Kim et al. · Microelectronics Reliability · 2009 · 84 citations

Engineering, Computer Engineering, Electrical Engineering +14

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Saibal Mukhopadhyay, Rahul Rao, Jae‐Joon Kim et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009 · 78 citations

Engineering, Computer Engineering, Electrical Engineering +17

Efficient techniques for gate leakage estimation

Rahul Rao, J.L. Burns, Anirudh Devgan et al. · 2003 · 73 citations

Engineering, Computer Engineering, Electrical Engineering +14

High-performance SRAM in nanoscale CMOS: Design challenges and techniques

Ching-Te Chuang, Saibal Mukhopadhyay, Jae‐Joon Kim et al. · Records of the IEEE International Workshop on Memory Technology, Design, and Testing · 2007 · 63 citations

Engineering, Computer Engineering, Electrical Engineering +17