Improving the ESD self-protection capability of integrated power NLDMOS arrays

Abstract

The self-protection capability (SPC) of integrated power arrays in ESD regimes has been studied for the case of integrated 100 V NLDMOS arrays in a BCD process. A new practical methodology for array comparison has been experimentally validated in order to take into account both gate coupling and avalanche current effects. Using TLP and electrical test methods, two orders of magnitude improvement of SPC has been demonstrated by implementation changes to array design. The effects of the Pbody shading and the drain region design have been quantified and analyzed by numerical simulation, and their physical nature has been discussed.