Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Kaustav Banerjee, S.J. Souri, Pawan Kapur et al. · Proceedings of the IEEE · 2001 · 1K citations

Engineering, Computer Engineering, Electrical Engineering +17

Demystifying 3D ICs: The Pros and Cons of Going Vertical

W. Rhett Davis, John Wilson, Stephen Mick et al. · IEEE Design & Test of Computers · 2005 · 832 citations

Engineering, Computer Engineering, Electrical Engineering +17

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

P. Morrow, Choon-Ho Park, Shriram Ramanathan et al. · IEEE Electron Device Letters · 2006 · 167 citations

Engineering, Computer Engineering, Electrical Engineering +17

Multiple Si layer ICs

S.J. Souri, Kaustav Banerjee, Amit Mehrotra et al. · 2000 · 107 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Predicting the Performance of a 3D Processor-Memory Chip Stack

Philip Jacob, Okan Erdogan, Aamir Zia et al. · IEEE Design & Test of Computers · 2005 · 59 citations

Engineering, Computer Engineering, Computer Science +17