High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation

A low-voltage triggering SCR for on-chip ESD protection at output and input pads

Amitava Chatterjee, T. Polgreen · IEEE Electron Device Letters · 1991 · 242 citations

Hardware Security, Electrical Engineering, Engineering +9

Analysis of lateral DMOS power devices under ESD stress conditions

M. Mergens, W. Wilkening, S. Mettler et al. · IEEE Transactions on Electron Devices · 2000 · 124 citations

Transmission Line Pulse, Electrical Engineering, Human Body Model +8

GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes

Russ, Mergens, Verhaege et al. · Electrical Overstress/Electrostatic Discharge Symposium · 2001 · 89 citations

Electrical Engineering, Ggnmos Triggered Silicon, Engineering +5

Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

Jie Wu, P. Juliano, Elyse Rosenbaum · 2002 · 78 citations

Materials Engineering, Electrical Engineering, Semiconductor Device +14

Using an SCR as ESD protection without latch-up danger

Guido Notermans, F.G. Kuper, Jan-Marc Luchies · Microelectronics Reliability · 1997 · 45 citations

Trusted Execution Environment, Hardware Security Solution, Esd Protection