Quantification and mitigation strategies of neutron induced soft-errors in CMOS devices and components

Abstract

As semiconductor device scaling is on-going far below 100 nm design rule, terrestrial neutron-induced soft-error typically in SRAMs is predicted to be worsen furthermore. Moreover, novel failure modes that may be more serious than those in memory soft-error are recently being reported. Therefore, necessity of implementing mitigation techniques is rapidly growing at the design phase, together with development of advanced detection and quantification techniques. The most advanced such techniques are reviewed and discussed.