EngineeringComputer EngineeringDigital DesignComputer ArchitectureLow-power DesignSystem-on-chip DesignClock Distribution NetworksClock ManagementCmos Circuit DesignLogic SynthesisTiming AnalysisVery-large-scale Integration LayoutClock Buffer DesignClock Distribution DesignClock Network ArchitectureClock Network SynthesisClock Tree SynthesisHigh PerformanceSkew DistributionSkew Mitigation
Using clock tree synthesis to create a high performance clocking network during layout requires the implementation of an active buffer distribution that is a design and technology specific trade-off between skew sensitivity, clock insertion delay, and simultaneously switching power dissipation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>