Transistor Stacking

Transistor Stacking is a leakage power reduction technique in which transistors are connected in series within a logic gate to increase the effective threshold voltage of the stack, thereby reducing subthreshold leakage current when at least one transistor in the stack is in the off state.

55

Publications

1.8K

Citations

301

Authors

77

Institutions

Publications per year

2017–2026

21

Authors

301

  1. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    4 publications · 131 citations

    4

    h-index

  2. YZ
    Yongkui Zhang

    Chinese Academy of Sciences, China

    2 publications · 164 citations

    2

    h-index

  3. RN
    Renato Negra

    RWTH Aachen University, Germany

    2 publications · 41 citations

    2

    h-index

  4. SM
    Saibal Mukhopadhyay

    Georgia Institute of Technology, United States

    2 publications · 48 citations

    2

    h-index

  5. SN
    S. Narendra

    Intel (United States), United States

    2 publications · 27 citations

    2

    h-index

1–5 of 301

Venues

  1. IEEE Electron Device Letters

    4 publications · 124 citations

    4

    h-index

  2. IEEE Journal of Solid-State Circuits

    4 publications · 98 citations

    4

    h-index

  3. 2

    h-index

  4. 2

    h-index

  5. 1

    h-index

1–5