Transistor Stacking
Transistor Stacking is a leakage power reduction technique in which transistors are connected in series within a logic gate to increase the effective threshold voltage of the stack, thereby reducing subthreshold leakage current when at least one transistor in the stack is in the off state.
55
Publications
1.8K
Citations
301
Authors
77
Institutions
Publications per year
2017–2026
21
Parents
55
New structure transistors for advanced technology node CMOS ICs
Qingzhu Zhang, Yongkui Zhang, Yan-Na Luo et al. · National Science Review · 2024 · 139 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
Leakage power reduction in low-voltage CMOS designs
Kaushik Roy · 2002 · 57 citations
1–5 of 55
301
4
h-index
2
h-index
2
h-index
2
h-index
2
h-index
1–5 of 301
77
Purdue University West Lafayette
West Lafayette, United States
6 h-index
10 publications
273 citations
Institute of Microelectronics
Beijing, China
4 h-index
27 publications
1.2K citations
RWTH Aachen University
Aachen, Germany
2 h-index
6 publications
108 citations
Carnegie Mellon University
Pittsburgh, United States
2 h-index
4 publications
184 citations
Georgia Institute of Technology
Atlanta, United States
2 h-index
5 publications
144 citations

Chinese Academy of Sciences
Beijing, China
2 h-index
18 publications
906 citations

Lund University
Lund, Sweden
2 h-index
5 publications
96 citations
University of Chinese Academy of Sciences
Beijing, China
2 h-index
9 publications
453 citations
1–8 of 77
4 publications · 124 citations
4
h-index
4 publications · 98 citations
4
h-index
2 publications · 47 citations
2
h-index
2 publications · 60 citations
2
h-index
1 publications · 22 citations
1
h-index
1–5