Subthreshold Slope Engineering
Subthreshold Slope Engineering is a device-level optimization methodology in semiconductor electronics that specifically tailors the subthreshold current-voltage characteristics of a transistor to minimize the subthreshold swing, thereby enhancing gate control and enabling aggressive device scaling beyond classical limits.
33
Publications
1.8K
Citations
237
Authors
47
Institutions
Publications per year
2017–2026
13
Parents
33
1–5 of 33
237
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National Institute of Advanced Industrial Science and Technology, Japan
2 publications · 94 citations
2
h-index
1–5 of 237
47
IMEC
Leuven, Belgium
3 h-index
50 publications
2.5K citations
STMicroelectronics (France)
Montrouge, France
2 h-index
3 publications
37 citations

Hanyang University
Seoul, South Korea
2 h-index
6 publications
195 citations
CEA Grenoble
Grenoble, France
2 h-index
6 publications
131 citations
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
Paris, France
2 h-index
6 publications
131 citations

Université Grenoble Alpes
Saint-Martin-d'Hères, France
2 h-index
11 publications
220 citations
Institute of Microelectronics
Beijing, China
2 h-index
16 publications
668 citations

Peking University
Beijing, China
2 h-index
16 publications
668 citations
1–8 of 47
8 publications · 353 citations
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3 publications · 110 citations
3
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2 publications · 52 citations
2
h-index
1 publications · 118 citations
1
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1 publications · 12 citations
1
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