Subthreshold Slope Engineering

Subthreshold Slope Engineering is a device-level optimization methodology in semiconductor electronics that specifically tailors the subthreshold current-voltage characteristics of a transistor to minimize the subthreshold swing, thereby enhancing gate control and enabling aggressive device scaling beyond classical limits.

33

Publications

1.8K

Citations

237

Authors

47

Institutions

Publications per year

2017–2026

13

Authors

237

  1. OK
    Oh‐Kyong Kwon

    Hanyang University, South Korea

    2 publications · 65 citations

    2

    h-index

  2. QH
    Qianqian Huang

    Peking University, China

    2 publications · 76 citations

    2

    h-index

  3. RH
    Ru Huang

    Peking University, China

    2 publications · 76 citations

    2

    h-index

  4. MJ
    M. Jurczak

    IMEC, Belgium

    2 publications · 61 citations

    2

    h-index

  5. MM
    Meishoku Masahara

    National Institute of Advanced Industrial Science and Technology, Japan

    2 publications · 94 citations

    2

    h-index

1–5 of 237

Venues

  1. IEEE Electron Device Letters

    8 publications · 353 citations

    8

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  2. IEEE Transactions on Electron Devices

    3 publications · 110 citations

    3

    h-index

  3. Solid-State Electronics

    2 publications · 52 citations

    2

    h-index

  4. IEEE Transactions on Nanotechnology

    1 publications · 118 citations

    1

    h-index

  5. 1

    h-index

1–5