Scan Chain Placement

Scan Chain Placement is a physical design methodology in Very-Large-Scale Integration layout that determines the optimal spatial arrangement of scan flip-flops and their interconnections to minimize routing overhead, timing degradation, and test application time during structural testing.

Publications

2.1K

Citations

164

Authors

Institutions

Publications per year

2017–2026

Parents

Very-large-scale Integration Layout

Publications

A graph placement methodology for fast chip design

Azalia Mirhoseini, Anna Goldie, Mustafa Ege Yazgan et al. · Nature · 2021 · 581 citations

Engineering, Computer Engineering, Computer Science +14

Using a single input to support multiple scan chains

Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang · 1998 · 195 citations

Computing, Computer Engineering, Computer Science +10

Power driven chaining of flip-flops in scan architectures

Yannick Bonhomme, Patrick Girard, C. Landrault et al. · 2003 · 108 citations

Engineering, Computer Engineering, Computer Science +17

Efficient scan chain design for power minimization during scan testing under routing constraint

Y. Borthomme, Patrick Girard, L. Guiller et al. · 2004 · 95 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Optimal configuring of multiple scan chains

Sridhar Narayanan, Rajesh K. Gupta, M.A. Breuer · IEEE Transactions on Computers · 1993 · 60 citations

Engineering, Computer Engineering, Computer Science +15

1–5 of 50

Authors

164

SR
S.M. Reddy
University of Iowa, United States
4 publications · 77 citations
4
h-index
NN
Nicola Nicolici
McMaster University, Canada
3 publications · 47 citations
3
h-index
PG
Patrick Girard
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France
2 publications · 203 citations
2
h-index
YH
Yu Huang
Mentor Technologies, United States
2 publications · 43 citations
2
h-index
YZ
Yi Zou
The University of Texas at Austin, United States
2 publications · 25 citations
2
h-index

1–5 of 164

Institutions

1–8 of 57

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2 publications · 35 citations
2
h-index
IEEE Transactions on Computers
2 publications · 71 citations
2
h-index
IEEE/ACM International Conference on Computer-Aided Design
Conference · 2 publications · 34 citations
2
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2 publications · 50 citations
2
h-index
Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)
Conference · 1 publications · 10 citations
1
h-index

1–5