Parasitic Capacitance Reduction

Parasitic Capacitance Reduction is a semiconductor device optimization technique that minimizes unintended capacitive coupling within high-frequency structures by altering physical layout or material properties to enhance device speed and performance.

738

Publications

25.1K

Citations

3.1K

Authors

601

Institutions

Publications per year

2017–2026

179

Authors

3.1K

  1. CL
    Chun‐Yu Lin

    National Yang Ming Chiao Tung University, Taiwan

    10 publications · 281 citations

    10

    h-index

  2. MK
    Ming‐Dou Ker

    National Yang Ming Chiao Tung University, Taiwan

    9 publications · 245 citations

    9

    h-index

  3. HF
    Haigang Feng

    Illinois Institute of Technology, United States

    7 publications · 157 citations

    7

    h-index

  4. SW
    Shuo Wang

    University of Florida, United States

    7 publications · 283 citations

    7

    h-index

  5. MA
    Mohammad Ali Saket

    University of British Columbia, Canada

    5 publications · 401 citations

    5

    h-index

1–5 of 3.1K

Venues

  1. IEEE Transactions on Electron Devices

    52 publications · 2K citations

    27

    h-index

  2. IEEE Electron Device Letters

    45 publications · 1.5K citations

    24

    h-index

  3. IEEE Transactions on Power Electronics

    24 publications · 1.3K citations

    23

    h-index

  4. IEEE Journal of Solid-State Circuits

    23 publications · 1.2K citations

    19

    h-index

  5. 18

    h-index

1–5