Parasitic Capacitance Reduction
Parasitic Capacitance Reduction is a semiconductor device optimization technique that minimizes unintended capacitive coupling within high-frequency structures by altering physical layout or material properties to enhance device speed and performance.
738
Publications
25.1K
Citations
3.1K
Authors
601
Institutions
Publications per year
2017–2026
179
738
The class-E/F family of ZVS switching amplifiers
S. Kee, Ichiro Aoki, Ali Hajimiri et al. · IEEE Transactions on Microwave Theory and Techniques · 2003 · 292 citations
High-voltage, high-power, ZVS, full-bridge PWM converter employing an active snubber
Juan Sabate, V. Vlatkovic, R.B. Ridley et al. · 2002 · 203 citations
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National Yang Ming Chiao Tung University
Hsinchu, Taiwan
16 h-index
62 publications
2.2K citations
Stanford University
Stanford, United States
14 h-index
67 publications
2.8K citations
Georgia Institute of Technology
Atlanta, United States
14 h-index
61 publications
2.1K citations
IBM (United States)
Armonk, United States
13 h-index
102 publications
3.8K citations
Massachusetts Institute of Technology
Cambridge, United States
13 h-index
34 publications
1.9K citations
University of California, Los Angeles
Los Angeles, United States
13 h-index
26 publications
878 citations
Texas Instruments (United States)
Dallas, United States
12 h-index
38 publications
965 citations
Fujitsu (Japan)
Kawasaki, Japan
12 h-index
55 publications
2.8K citations
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52 publications · 2K citations
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45 publications · 1.5K citations
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24 publications · 1.3K citations
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23 publications · 1.2K citations
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19 publications · 1.1K citations
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