Optical Properties of Colloidal PbSe Nanocrystals

Hui Du, Chialing Chen, R. Krishnan, +5

Nano Letters

Luminescence LifetimesColloidal Pbse NanocrystalsOptical MaterialsEngineeringColloidal Nanocrystals +16

On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors

S. Mookerjea, R. Krishnan, Suman Datta, +1

IEEE Electron Device Letters

Electrical EngineeringSemiconductor DeviceEngineeringMiller CapacitanceTunneling Microscopy +9

Experimental demonstration of 100nm channel length In<inf>0.53</inf>Ga<inf>0.47</inf>As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications

S. Mookerjea, D. K. Mohata, R. Krishnan, +8

Device ModelingElectrical EngineeringSub XmlnsEngineeringExperimental Demonstration +8

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried, +51

High-performance Soi TechnologyEngineeringVlsi DesignComputer ArchitectureInterconnect (Integrated Circuits) +14

Toward Increasing FPGA Lifetime

Suresh Srinivasan, R. Krishnan, Prasanth Mangalagiri, +4

IEEE Transactions on Dependable and Secure Computing

EngineeringHardware AlgorithmComputer ArchitectureHardware SecurityTransient Error Susceptibility +16

A 7nm CMOS technology platform for mobile and high performance compute application

B. Jagannathan, Akihisa Ogino, D. Jaeger, +149

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsHardware Systems +15

Polarization Surface-Charge Density of Single Semiconductor Quantum Rods

R. Krishnan, Megan A. Hahn, Zhiheng Yu, +3

Physical Review Letters

EngineeringSemiconductorsPolarization Surface-charge DensityNanoelectronicsNanometrology +16

Impact of aggressive fin width scaling on FinFET device characteristics

Xiaoli He, Jody Fronheiser, Pei Zhao, +16

Device ModelingElectrical EngineeringFinfet Device CharacteristicsEngineeringFin Width Scaling +8

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits

R. Ramanarayanan, V. Degalahal, R. Krishnan, +5

IEEE Transactions on Dependable and Secure Computing

Logic LevelsEngineeringVlsi DesignCombinational CircuitsComputer Architecture +19

Scaling deep trench based eDRAM on SOI to 32nm and Beyond

G. Wang, D. Anand, Nauman Zafar Butt, +24

Electrical EngineeringEngineeringVlsi DesignDeep TrenchNanoelectronics +7