S. Siddiqui

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

Ruijie Xie, P. Montanini, Kerem Akarvardar et al. · 2016 · 139 citations

Engineering, Electron-beam Lithography, Finfet Technology +18

High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 128 citations

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Siddarth Krishnan, U. Kwon, N. Moumen et al. · 2011 · 81 citations

Sige Channels, Low Power Applications, Engineering +16

Future on-chip interconnect metallization and electromigration

Chunhua Hu, James J. Kelly, Huai Huang et al. · 2018 · 69 citations

Materials Science, Materials Engineering, Electrical Engineering +15

Tungsten and cobalt metallization: A material study for MOL local interconnects

V. Kamineni, M. Raymond, S. Siddiqui et al. · 2016 · 63 citations

Mol Local Interconnects, Engineering, Cvd W-based Metallization +21