S. Siddiqui - Concepedia

Author

S. Siddiqui

Also Known As

S Siddiqui, S. Siddiqui, S.H. Siddiqui, Shahab Siddiqui, Shayan Qayoom Siddiqui, Sheraz Hussain Siddiqui, Subhana Ayesha Siddiqui

Publications

805

Citations

H-Index

Concepts

All Affiliations

GlobalFoundries (United States)IBM (United States)STMicroelectronics (United States)

About

S. Siddiqui is an author at GlobalFoundries (United States) specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	11	11	574
2	Applied Physics	9	9	534
3	Computer Engineering	4	4	156
4	Business	1	1	21
5	Computer Science	1	1	21

S. Siddiqui

Publications

714

Citations

H-Index

Page 1

	Year	Citations
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels Ruijie Xie, P. Montanini, Kerem Akarvardar, EngineeringElectron-beam LithographyFinfet TechnologyMechanical EngineeringWafer Scale Processing	2016	139
High performance 14nm SOI FinFET CMOS technology with 0.0174&#x00B5;m<sup>2</sup> embedded DRAM and 15 levels of Cu metallization C-H. Lin, B. Greene, J. Cai,	2014	128
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications Siddarth Krishnan, U. Kwon, N. Moumen, Sige ChannelsLow Power ApplicationsEngineeringVlsi DesignIntegrated Circuits	2011	81
Future on-chip interconnect metallization and electromigration Chunhua Hu, James J. Kelly, Huai Huang, Materials ScienceMaterials EngineeringElectrical EngineeringElectromigration TechniqueCu Liner	2018	69
Tungsten and cobalt metallization: A material study for MOL local interconnects V. Kamineni, M. Raymond, S. Siddiqui, Mol Local InterconnectsEngineeringCvd W-based MetallizationWafer Scale ProcessingAdvanced Packaging (Semiconductors)	2016	63
Experimental study of nanoscale Co damascene BEOL interconnect structures James J. Kelly, Jinai Chen, Huai Huang, EngineeringNm Node DimensionsMaterial InnovationCo Line ResistanceInterconnect (Integrated Circuits)	2016	51
Electromigration and resistivity in on-chip Cu, Co and Ru damascene nanowires Chunhua Hu, James J. Kelly, J. H-C Chen, EngineeringInterconnect (Integrated Circuits)NanoelectronicsElectronic PackagingCo Cap	2017	43
BEOL process integration for the 7 nm technology node T. Standaert, Genevieve Beique, H.-C. Chen, EngineeringElectron-beam LithographyDevice IntegrationBeol Process IntegrationSelective Co Cap	2016	35
Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness Min Dai, Yanfeng Wang, J. Shepard, Journal of Applied Physics Materials ScienceMaterials EngineeringElectrical EngineeringEngineeringPlasma N2	2013	29
A comparative study of strain and Ge content in Si<inf>1−x</inf>Ge<inf>x</inf> channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs C. H. Lee, Shinichi Mochizuki, Richard G. Southwick, Materials EngineeringSemiconductor TechnologyElectrical EngineeringEngineeringBuffer Layer Finfets	2017	24

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