Gyoyoung Jin

Scaling and reliability of NAND flash devices

Young‐Woo Park, Seong Soon Cho, Gyoyoung Jin et al. · 2014 · 66 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

Kyomin Sohn, Won-Joo Yun, Reum Oh et al. · IEEE Journal of Solid-State Circuits · 2016 · 62 citations

Engineering, Computer Engineering, High-performance Computing +15

Novel 4F<sup>2</sup> DRAM cell with Vertical Pillar Transistor(VPT)

Hyun-Woo Chung, Huijung Kim, Hyun-Gi Kim et al. · 2011 · 47 citations

Engineering, Electrical Engineering, Materials Science +11

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Chang‐Kyo Lee, Yoon-Joo Eom, Jin‐Hee Park et al. · 2017 · 44 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo et al. · IEEE Journal of Solid-State Circuits · 2018 · 40 citations

Engineering, Computer Engineering, Computer Architecture +16