H. Aochi

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Hidetake Tanaka, M. Kido, K. Yahashi et al. · 2007 · 585 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 45-ns 16-Mbit DRAM with triple-well structure

Shosuke Fujii, M. Ogihara, Motoki Shimizu et al. · IEEE Journal of Solid-State Circuits · 1989 · 43 citations

Engineering, Computer Engineering, Electrical Engineering +9

A 45 ns 16 Mb DRAM with triple-well structure

S. Fujii, M. Ogihara, Motoki Shimizu et al. · 2003 · 30 citations

Engineering, Computer Engineering, Electrical Engineering +10

A fully planarized 0.25 μm CMOS technology for 256 Mbit DRAM and beyond

G. Bronner, H. Aochi, M. Gall et al. · 2002 · 25 citations

Engineering, Electrical Engineering, Microelectronics +16

Fin-Array-FET on bulk silicon for sub-100 nm trench capacitor DRAM

Ryoichi Katsumata, N. Tsuda, J. Idebuchi et al. · 2004 · 17 citations

Engineering, Electrical Engineering, Electronic Materials +14