IEEE Journal of Solid-State Circuits · 1989 · 43 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesCmos Circuit DesignIntegrated Circuit DesignMemory HierarchyMemory Subsystem DesignMemory Array ArchitectureMemory Circuit Design
A 16-Mbit DRAM fabricated with a 0.6- mu m triple-well CMOS technology on an n-substrate is described. The fast RAS access time of 45 ns has been achieved by the use of a triple-well structure, an optimized chip architecture, and a decoded word-line bootstrap driver. An advanced trench capacitor cell of area 4.8 mu m/sup 2/ is realized by introducing a quarter-pitched memory array arrangement. A three-way voltage-down conversion system enhances RAM performance as well as reliability. The RAM measures 7.87*17.4 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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An experimental 1-Mbit BiCMOS DRAM
G. Kitsukawa, R. Hori, Y. Kawajiri et al. · IEEE Journal of Solid-State Circuits · 1987 · 30 citations
Engineering, Computer Engineering, Electrical Engineering +17
An Experimental 16mb Cmos dram Chip with a 100mhz Serial Read/Write Mode
Watanabe †↑, Itoh, Sakui et al. · 1988 · 24 citations
Engineering, Computer Engineering, Electrical Engineering +14