A 45-ns 16-Mbit DRAM with triple-well structure

Abstract

A 16-Mbit DRAM fabricated with a 0.6- mu m triple-well CMOS technology on an n-substrate is described. The fast RAS access time of 45 ns has been achieved by the use of a triple-well structure, an optimized chip architecture, and a decoded word-line bootstrap driver. An advanced trench capacitor cell of area 4.8 mu m/sup 2/ is realized by introducing a quarter-pitched memory array arrangement. A three-way voltage-down conversion system enhances RAM performance as well as reliability. The RAM measures 7.87*17.4 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>