2003 · 30 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesMemory DevicesMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignMemory Array ArchitectureMemory Circuit DesignSense Amplifier Design
The authors describe a 16-Mb DRAM (dynamic RAM) fabricated with a triple-well CMOS technology that enables optimum choice of well bias. With this technology, an optimized chip architecture, and a p-channel load word-line bootstrap driver incorporating a predecoder a 45-ns row-access-strobe access time is achieved. The memory cell is in a quarter-pitched arrangement combined with an interdigitated bit-line/shared-sense-amplifier scheme. This overcomes the difficulty of defining capacitor-plate poly in a scaled-down trench or buried-stacked-capacitor cell. The output waveform of the RAM is shown. The features of the 16M DRAM are summarized. It is capable of fast page, static column, or nibble operation and -*1- or *4-bit organization, determined by the choice of bonding configuration.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
1
An Experimental 16mb Cmos dram Chip with a 100mhz Serial Read/Write Mode
Watanabe †↑, Itoh, Sakui et al. · 1988 · 24 citations
Engineering, Computer Engineering, Electrical Engineering +14