M. Hussein

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

Scott E. Thompson, N. Anand, M Armstrong et al. · 2003 · 243 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

C. Auth, S. Balakrishnan, M. Bost et al. · 2005 · 230 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

S. Tyagi, Morteza S. Alavi, R. Bigwood et al. · 2002 · 150 citations

Engineering, Computer Engineering, Electrical Engineering +13

A high performance 180 nm generation logic technology

Shih‐Chi Yang, Sally Ahmed, B. Arcot et al. · 2002 · 89 citations

Engineering, Computer Engineering, Electrical Engineering +17

Materials' Impact on Interconnect Process Technology and Reliability

M. Hussein, Jie He · IEEE Transactions on Semiconductor Manufacturing · 2005 · 67 citations

Engineering, Materials Engineering, Materials Science +17