J. Holt - Concepedia

Author

J. Holt

Also Known As

Holt, J. R., Holt, Judson R.; Jain, Vibhor; Johnson, Jeffrey B.; Pekarik, John J., J Holt, J. HOLT, J. Holt, J. R. Holt, J.R. Holt, Judson Holt, Judson R. Holt, Judson Robert Holt

Publications

1.2K

Citations

H-Index

Concepts

All Affiliations

IBM (United States)IBM Research - Thomas J. Watson Research Center GlobalFoundries (United States)Argonne National Laboratory Massachusetts Institute of Technology

About

J. Holt is an author at IBM (United States) specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	19	29	1.1K
2	Applied Physics	15	22	738
3	Natural Sciences	3	3	42
4	Chemistry	3	3	42
5	Medicine	2	2	144

J. Holt

Publications

1.1K

Citations

H-Index

Page 1

	Year	Citations
High-resolution three-dimensional structural microscopy by single-angle Bragg ptychography S. O. Hruszkewycz, Marc Allain, Martin V. Holt, Nature Materials Materials ScienceEngineeringMicroscopyMedicineMicroscopy Method	2016	133
High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography P. Agnello, T. Ivers, C. Warm, EngineeringVlsi DesignEnhanced StrainPorous Low-k BeolIntegrated Circuits	2006	115
Quantitative Nanoscale Imaging of Lattice Distortions in Epitaxial Semiconductor Heterostructures Using Nanofocused X-ray Bragg Projection Ptychography S. O. Hruszkewycz, Martin V. Holt, Conal E. Murray, Nano Letters Nanoscale Lattice StrainEngineeringMicroscopyLattice DistortionsSemiconductor Nanostructures	2012	94
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL P. Chang, C. Ortolland, David Fried, High-performance Soi TechnologyEngineeringVlsi DesignComputer ArchitectureInterconnect (Integrated Circuits)	2012	89
Strain Imaging of Nanoscale Semiconductor Heterostructures with X-Ray Bragg Projection Ptychography Martin V. Holt, S. O. Hruszkewycz, Conal E. Murray, Physical Review Letters Materials ScienceEngineeringPhysicsMicroscopyLattice Rotation	2014	64
A 7nm CMOS technology platform for mobile and high performance compute application B. Jagannathan, Akihisa Ogino, D. Jaeger, EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsHardware Systems	2017	58
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper B. Greene, Qingqing Liang, K. Amarnath, Symposium on VLSI Technology EngineeringVlsi DesignNm Ground RulesHigh Performance 32NmIntegrated Circuits	2006	40
Gate Length and Performance Scaling of Undoped-Body Extremely Thin SOI MOSFETs A. Majumdar, Xinlin Wang, Arvind Kumar, IEEE Electron Device Letters Device ModelingPerformance ScalingElectrical EngineeringGate LengthEngineering	2009	37
High-Performance Undoped-Body 8-nm-Thin SOI Field-Effect Transistors Amlan Majumdar, Zhibin Ren, J.W. Sleight, IEEE Electron Device Letters Electrical EngineeringEngineeringField-effect TransistorsNanoelectronicsElectronic Engineering	2008	37
On the integration of CMOS with hybrid crystal orientations Min Yang, V. Chan, S.H. Ku, Electrical EngineeringEngineeringVlsi DesignIntegration IssuesNanoelectronics	2004	32

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