S. Gannavaram

A 32nm SoC platform technology with 2<sup>nd</sup> generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

C.-H. Jan, M. Agostinelli, Markus J. Buehler et al. · 2009 · 75 citations

Engineering, Vlsi Design, Computer Architecture +20

Low temperature (800°C) recessed junction selective silicon-germanium source/drain technology for sub-70 nm CMOS

S. Gannavaram, N. Pesovic, Cem Öztürk · 2002 · 70 citations

Sub-70 Nm Cmos, Semiconductor Technology, Electrical Engineering +12

An advanced low power, high performance, strained channel 65nm technology

S. Tyagi, C. Kenyon, S.-H. Lee et al. · 2005 · 63 citations

Low-power Electronics, Electrical Engineering, Enhanced Transistor Performance +6

A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

I. Post, M.S. Akbar, G. Curello et al. · 2006 · 57 citations

Low-power Electronics, Pmos Transistors, Electrical Engineering +11

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

C.-H. Jan, Peng Bai, S. Biswas et al. · 2008 · 45 citations

Robust Reliability, Engineering, Vlsi Design +17