Low temperature (800°C) recessed junction selective silicon-germanium source/drain technology for sub-70 nm CMOS

Abstract

We present a novel, low-temperature source/drain junction and contact formation technology applicable to sub-70 nm CMOS. In this process, in-situ boron doped SiGe is selectively deposited at 500/spl deg/C in the source/drain windows recessed to the desired junction depth. The technology meets the NTRS roadmap requirements for (i) junction depth/sheet resistance (<100 /spl Omega//sq. for 30 nm junctions), (ii) ultra-low resistivity contacts (1.5/spl times/10/sup -8/ /spl Omega/-cm/sup 2/), (iii) excellent reverse leakage characteristics (less than 1% of the I/sub OFF/ budget), (iv) perfect box-shaped lateral abruptness and (v) thermal integration compatibility with high-k gate dielectrics using the conventional (gate-last) CMOS process flow.