10×10nm<sup>2</sup> Hf/HfO<inf>x</inf> crossbar resistive RAM with excellent performance, reliability and low-energy operation

B. Govoreanu, Gouri Sankar Kar, YY Chen, +18

Non-volatile MemoryResistive RamEngineeringExcellent PerformanceEmerging Memory Technology +15

Highly reliable TaO<inf>x</inf> ReRAM with centralized filament for 28-nm embedded application

Y. Hayakawa, A. Himeno, Ryo Yasuhara, +17

High Thermal StabilityCell StructureEngineeringEmerging Memory TechnologyComputer Architecture +18

Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

M.J.H. van Dal, Nadine Collaert, G. Doornbos, +22

EngineeringIntegrated CircuitsInterconnect (Integrated Circuits)Semiconductor DeviceWafer Scale Processing +16

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

K. von Arnim, E. Augendre, A.C. Pacha, +15

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignMixed-signal Integrated Circuit +9

A new complementary hetero-junction vertical Tunnel-FET integration scheme

R. Rooyackers, A. Vandooren, Anne S. Verhulst, +11

SemiconductorsWide-bandgap SemiconductorElectrical EngineeringSemiconductor TechnologyNew Integration Scheme +11

Record I<inf>ON</inf>/I<inf>OFF</inf> performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

Jérôme Mitard, Brice De Jaeger, Frederik Leys, +16

Record PerformanceElectrical EngineeringEngineeringVlsi DesignBias Temperature Instability +7

High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants

Geert Hellings, Geert Hellings, Jérôme Mitard, +13

IEEE Electron Device Letters

Semiconductor TechnologyElectrical EngineeringEngineeringRf SemiconductorBoron Ldd Implants +8

Ge-Source Vertical Tunnel FETs Using a Novel Replacement-Source Integration Scheme

R. Rooyackers, A. Vandooren, Anne S. Verhulst, +12

IEEE Transactions on Electron Devices

Trap-assisted TunnelingElectrical EngineeringPoint TunnelingEngineeringNanoelectronics +6

Double patterning for 32nm and below: an update

Jo Finders, Mircea Dusa, Bert Vleeming, +5

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Cdu ControlPhysical Design (Electronics)Array ComputingEngineeringElectron-beam Lithography +13

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

Julien Beynet, Patrick Wong, Andy Miller, +9

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE